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DP80390 pipelined high performance microcontroller instructions set details ver 3.10
DP80390 instructions set details - 2 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. contents 1. overview ____________________________________________________________ 7 1.1. document structure. ________________________________________________________7 2. instructions set brief___________________________________________________ 7 2.1. instruction set notes ________________________________________________________7 2.2. instruction set brief ? functional order _________________________________________8 2.2.1. arithmetic operations ___________________________________________________________ 8 2.2.2. logic operations _______________________________________________________________ 9 2.2.3. boolean manipulation___________________________________________________________ 9 2.2.4. data transfers________________________________________________________________ 10 2.2.5. program branches ____________________________________________________________ 11 2.3. instruction set brief ? hexadecimal order ______________________________________12 3. instructions set details ________________________________________________ 15 3.1. acall * _________________________________________________________________15 3.1.1. large _____________________________________________________________________ 15 3.1.2. flat ______________________________________________________________________ 16 3.2. add_____________________________________________________________________17 3.2.1. add a, rn __________________________________________________________________ 17 3.2.2. add a, direct ________________________________________________________________ 17 3.2.3. add a, @ri _________________________________________________________________ 18 3.2.4. add a, #data ________________________________________________________________ 18 3.3. addc ___________________________________________________________________19 3.3.1. addc a, rn _________________________________________________________________ 19 3.3.2. addc a, direct _______________________________________________________________ 19 3.3.3. addc a, @ri________________________________________________________________ 20 3.3.4. addc a, #data_______________________________________________________________ 20 3.4. ajmp * __________________________________________________________________21 3.4.1. large _____________________________________________________________________ 21 3.4.2. flat ______________________________________________________________________ 22 3.5. anl _____________________________________________________________________23 3.5.1. anl a, rn __________________________________________________________________ 23 3.5.2. anl a, direct ________________________________________________________________ 23 3.5.3. anl a, @ri _________________________________________________________________ 24 3.5.4. anl a, #data ________________________________________________________________ 24 3.5.5. anl direct, a ________________________________________________________________ 24 3.5.6. anl direct, #data _____________________________________________________________ 24 3.5.7. anl c, bit___________________________________________________________________ 25 3.5.8. anl c, /bit __________________________________________________________________ 25 3.6. cjne ____________________________________________________________________26 3.6.1. cjne a, direct, rel ____________________________________________________________ 26 3.6.2. cjne a, #data, rel ____________________________________________________________ 27 3.6.3. cjne rn, #data, rel___________________________________________________________ 27 3.6.4. cjne @ri, #data, rel __________________________________________________________ 28 3.7. clr _____________________________________________________________________29 3.7.1. clr a______________________________________________________________________ 29 3.7.2. clr bit ____________________________________________________________________ 29 3.7.3. clr c _____________________________________________________________________ 30 3.8. cpl _____________________________________________________________________31 3.8.1. cpl a______________________________________________________________________ 31 3.8.2. cpl bit _____________________________________________________________________ 31
DP80390 instructions set details - 3 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.8.3. cpl c______________________________________________________________________ 32 3.9. da ______________________________________________________________________33 3.10. dec ___________________________________________________________________34 3.10.1. dec a _____________________________________________________________________ 34 3.10.2. dec rn ____________________________________________________________________ 34 3.10.3. dec direct __________________________________________________________________ 35 3.10.4. dec @ri ___________________________________________________________________ 35 3.11. div____________________________________________________________________36 3.12. djnz __________________________________________________________________37 3.12.1. djnz rn, rel_________________________________________________________________ 37 3.12.2. djnz direct, rel ______________________________________________________________ 38 3.13. inc ___________________________________________________________________39 3.13.1. inc a ______________________________________________________________________ 39 3.13.2. inc rn _____________________________________________________________________ 39 3.13.3. inc direct ___________________________________________________________________ 40 3.13.4. inc @ri ____________________________________________________________________ 40 3.13.5. inc dptr* __________________________________________________________________ 40 3.14. jb ____________________________________________________________________41 3.15. jbc ___________________________________________________________________42 3.16. jc ____________________________________________________________________43 3.17. jmp* __________________________________________________________________44 3.18. jnb ___________________________________________________________________45 3.19. jnc ___________________________________________________________________46 3.20. jnz ___________________________________________________________________47 3.21. jz ____________________________________________________________________48 3.22. lcall * _______________________________________________________________49 3.22.1. large _____________________________________________________________________ 49 3.22.2. flat ______________________________________________________________________ 50 3.23. ljmp *_________________________________________________________________51 3.23.1. large _____________________________________________________________________ 51 3.23.2. flat ______________________________________________________________________ 51 3.24. mov __________________________________________________________________52 3.24.1. mov a, rn __________________________________________________________________ 52 3.24.2. mov a, direct ________________________________________________________________ 52 3.24.3. mov a, @ri_________________________________________________________________ 52 3.24.4. mov a, #data________________________________________________________________ 53 3.24.5. mov rn, a __________________________________________________________________ 53 3.24.6. mov rn, direct_______________________________________________________________ 53 3.24.7. mov rn, #data_______________________________________________________________ 53 3.24.8. mov direct, a ________________________________________________________________ 54 3.24.9. mov direct, rn_______________________________________________________________ 54 3.24.10. mov direct, direct ____________________________________________________________ 54 3.24.11. mov direct, @ri _____________________________________________________________ 54 3.24.12. mov direct, #data ____________________________________________________________ 55 3.24.13. mov @ri, a ________________________________________________________________ 55 3.24.14. mov @ri, direct _____________________________________________________________ 55 3.24.15. mov @ri, #data_____________________________________________________________ 55 3.24.16. mov c, bit _________________________________________________________________ 56 3.24.17. mov bit, c _________________________________________________________________ 56 3.24.18. mov dptr, #data16 - large__________________________________________________ 57
DP80390 instructions set details - 4 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.24.19. mov dptr, #data24* - flat___________________________________________________ 57 3.25. movc* ________________________________________________________________58 3.25.1. movc a, @a + dptr _________________________________________________________ 58 3.25.2. movc a, @a + pc ___________________________________________________________ 58 3.26. movx*_________________________________________________________________59 3.26.1. movx a, @ri _______________________________________________________________ 59 3.26.2. movx a, @dptr ____________________________________________________________ 59 3.26.3. movx @ri, a _______________________________________________________________ 60 3.26.4. movx @dptr, a ____________________________________________________________ 60 3.27. mul___________________________________________________________________61 3.28. nop___________________________________________________________________62 3.29. orl ___________________________________________________________________63 3.29.1. orl a, rn __________________________________________________________________ 63 3.29.2. orl a, direct ________________________________________________________________ 63 3.29.3. orl a, @ri _________________________________________________________________ 64 3.29.4. orl a, #data ________________________________________________________________ 64 3.29.5. orl direct, a ________________________________________________________________ 64 3.29.6. orl direct, #data _____________________________________________________________ 64 3.29.7. orl c, bit __________________________________________________________________ 65 3.29.8. orl c, /bit __________________________________________________________________ 65 3.30. pop* __________________________________________________________________66 3.30.1. large _____________________________________________________________________ 66 3.30.2. flat ______________________________________________________________________ 66 3.31. push* _________________________________________________________________67 3.31.1. large _____________________________________________________________________ 67 3.31.2. flat ______________________________________________________________________ 67 3.32. ret * __________________________________________________________________68 3.32.1. large _____________________________________________________________________ 68 3.32.2. flat ______________________________________________________________________ 68 3.33. reti * _________________________________________________________________69 3.33.1. large _____________________________________________________________________ 69 3.33.2. flat ______________________________________________________________________ 70 3.34. rl ____________________________________________________________________71 3.35. rlc ___________________________________________________________________72 3.36. rr ____________________________________________________________________73 3.37. rrc___________________________________________________________________74 3.38. setb __________________________________________________________________75 3.38.1. set b c ____________________________________________________________________ 75 3.38.2. set b bit ____________________________________________________________________ 75 3.39. sjmp__________________________________________________________________76 3.40. subb _________________________________________________________________77 3.40.1. subb a, rn _________________________________________________________________ 77 3.40.2. subb a, direct _______________________________________________________________ 77 3.40.3. subb a, @ri ________________________________________________________________ 78 3.40.4. subb a, #data _______________________________________________________________ 78 3.41. swap _________________________________________________________________79 3.42. xch ___________________________________________________________________80 3.42.1. xch a, rn __________________________________________________________________ 80 3.42.2. xch a, direct ________________________________________________________________ 80
DP80390 instructions set details - 5 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.42.3. xch a, @ri _________________________________________________________________ 80 3.43. xchd _________________________________________________________________81 3.44. xrl ___________________________________________________________________82 3.44.1. xrl a, rn __________________________________________________________________ 82 3.44.2. xrl a, direct ________________________________________________________________ 82 3.44.3. xrl a, @ ri_________________________________________________________________ 83 3.44.4. xrl a, #data ________________________________________________________________ 83 3.44.5. xrl direct, a ________________________________________________________________ 83 3.44.6. xrl direct, #data _____________________________________________________________ 83 4. contacts ____________________________________________________________ 84
DP80390 instructions set details - 6 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. tables table 1. notes on data addressing modes_______________________________________ 7 table 2. notes on program addressing modes ___________________________________ 7 table 3. arithmetic operations ________________________________________________ 8 table 4. logic operations ____________________________________________________ 9 table 5. boolean mani pulation ________________________________________________ 9 table 6. data transfer______________________________________________________ 10 table 7. program branches _________________________________________________ 11 table 8. instruction set brief in hexadecimal order________________________________ 14
DP80390 instructions set details - 7 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 1. o verview 1.1. d ocument structure . document contains brief description of DP80390 instructions . this manual is intended for design engineers who are planning to use t he DP80390 hdl core in conjunction with software assemb ler, compiler and debugger tools. 2. i nstructions set brief 2.1. i nstruction set notes the DP80390 has five different addressing m odes: immediate, direct, register, indirect and relative. in the immediate addressing m ode the data is contained in the opcode. by direct addressing an eight bit ad dress is a part of the opcode, by register addressing, a register is selected in the opcode for the operation. in t he indirect addressing mode, a register is selected in the opcode to point to the address used by the operation. the relative addressing mode is us ed for jump instructions. the following tables give a survey about the instruction set cycles of the DP80390 microcontroller core. one cycle is equal to one clock period . table 1 and table 2 contain notes for mnemonics used in instruction set tables. tables 3 - 7 show instruction hexadecimal codes, num ber of bytes and machine cycles that each instruction takes to execute. rn working register r0-r7 direct 128 internal ram locations, any special function registers @ri indirect internal or external ram location addressed by register r0 or r1 #data 8-bit constant included in instruction #data16 16-bit constant included as bytes 2 and 3 of instruction #data24 24-bit constant included as bytes 2,3 and 4 of instruction bit 256 software flags, any bit-addressable l/o pin, control or status bit a accumulator table 1. notes on data addressing modes addr24 destination address for lcall and ljmp may be anywhere within the 16 mb of program memory address space in flat mode. addr19 destination address for acall and ajmp will be within the same 512 kb page of program memory as the first byte of the following instruction in flat mode addr16 destination address for lcall and ljmp may be anywhere within the 64 kb of program memory address space in large mode. addr11 destination address for acall and ajmp will be within the same 2 kb page of program memory as the first byte of the following instruction in large mode rel sjmp and all conditional jumps include an 8-bit offset byte. range is +127/-128 bytes relative to the first byte of the following instruction table 2. notes on program addressing modes
DP80390 instructions set details - 8 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 2.2. i nstruction set brief ? functional order 2.2.1. a rithmetic operations mnemonic description code bytes cycles add a,rn add register to accumulator 0x28-0x2f 1 1 add a,direct add direct byte to accumulator 0x25 2 2 add a,@ri add indirect ram to accumulator 0x26-0x27 1 2 add a,#data add immediate data to accumulator 0x24 2 2 addc a,rn add register to accumulator with carry flag 0x38-0x3f 1 1 addc a,direct add direct byte to a with carry flag 0x35 2 2 addc a,@ri add indirect ram to a with carry flag 0x36-0x37 1 2 addc a,#data add immediate data to a with carry flag 0x34 2 2 subb a,rn subtract register from a with borrow 0x98-0x9f 1 1 subb a,direct subtract direct byte from a with borrow 0x95 2 2 subb a,@ri subtract indirect ra m from a with borrow 0x96-0x97 1 2 subb a,#data subtract immediate data from a with borrow 0x94 2 2 inc a increment accumulator 0x04 1 1 inc rn increment register 0x08-0x0f 1 2 inc direct increment direct byte 0x05 2 3 inc @ri increment indirect ram 0x06-0x07 1 3 dec a decrement accumulator 0x14 1 1 dec rn decrement register 0x18-0x1f 1 2 dec direct decrement direct byte 0x15 1 3 dec @ri decrement indirect ram 0x16-0x17 2 3 inc dptr increment data pointer 0xa3 1 1 mul a,b multiply a and b 0xa4 1 2 div a,b divide a by b 0x84 1 6 da a decimal adjust accumulator 0xd4 1 3 table 3. arithmetic operations
DP80390 instructions set details - 9 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 2.2.2. l ogic operations mnemonic description code bytes cycles anl a,rn and register to accumulator 0x58-0x5f 1 1 anl a,direct and direct byte to accumulator 0x55 2 2 anl a,@ri and indirect ram to accumulator 0x56-0x57 1 2 anl a,#data and immediate data to accumulator 0x54 2 2 anl direct,a and accumulator to direct byte 0x52 2 3 anl direct,#data and immediate data to direct byte 0x53 3 3 orl a,rn or register to accumulator 0x48-0x4f 1 1 orl a,direct or direct byte to accumulator 0x45 2 2 orl a,@ri or indirect ram to accumulator 0x46-0x47 1 2 orl a,#data or immediate data to accumulator 0x44 2 2 orl direct,a or accumulator to direct byte 0x42 2 3 orl direct,#data or immediate data to direct byte 0x43 3 3 xrl a,rn exclusive or register to accumulator 0x68-0x6f 1 1 xrl a,direct exclusive or direct byte to accumulator 0x65 2 2 xrl a,@ri exclusive or indirect ram to accumulator 0x66-0x67 1 2 xrl a,#data exclusive or immedi ate data to accumulator 0x64 2 2 xrl direct,a exclusive or accu mulator to direct byte 0x62 2 3 xrl direct,#data exclusive or imm ediate data to direct byte 0x63 3 3 clr a clear accumulator 0xe4 1 1 cpl a complement accumulator 0xf4 1 1 rl a rotate accumulator left 0x23 1 1 rlc a rotate accumulator left through carry 0x33 1 1 rr a rotate accumulator right 0x03 1 1 rrc a rotate accumulator right through carry 0x13 1 1 swap a swap nibbles within the accumulator 0xc4 1 1 table 4. logic operations 2.2.3. b oolean manipulation mnemonic description code bytes cycles clr c clear carry flag 0xc3 1 1 clr bit clear direct bit 0xc2 2 3 setb c set carry flag 0xd3 1 1 setb bit set direct bit 0xd2 2 3 cpl c complement carry flag 0xb3 1 1 cpl bit complement direct bit 0xb2 2 3 anl c,bit and direct bit to carry flag 0x82 2 2 anl c,/bit and complement of direct bit to carry 0xb0 2 2 orl c,bit or direct bit to carry flag 0x72 2 2 orl c,/bit or complement of direct bit to carry 0xa0 2 2 mov c,bit move direct bit to carry flag 0xa2 2 2 mov bit,c move carry flag to direct bit 0x92 2 3 table 5. boolean manipulation
DP80390 instructions set details - 10 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 2.2.4. d ata transfers mnemonic description code bytes cycles mov a,rn move register to accumulator 0xe8-0xef 1 1 mov a,direct move direct byte to accumulator 0xe5 2 2 mov a,@ri move indirect ram to accumulator 0xe6-0xe7 1 2 mov a,#data move immediate data to accumulator 0x74 2 2 mov rn,a move accumulator to register 0xf8-0xff 1 1 mov rn,direct move direct byte to register 0xa8-0xaf 2 3 mov rn,#data move immediate data to register 0x78-0x7f 2 2 mov direct,a move accumulator to direct byte 0xf5 2 2 mov direct,rn move register to direct byte 0x88-8f 2 2 mov direct1,direct2 move direct byte to direct byte 85 3 3 mov direct,@ri move indirect ram to direct byte 86-87 2 3 mov direct,#data move immediate data to direct byte 75 3 3 mov @ri,a move accumulator to indirect ram f6-f7 1 2 mov @ri,direct move direct byte to indirect ram a6-a7 2 3 mov @ri,#data move immediate data to indirect ram 76-77 2 2 mov dptr,#data16 load 16-bit constant into active dph and dpl in large mode 90 3 3 mov dptr,#data24 load 24-bit constant into active dpx, dph and dpl in flat mode 90 4 4 movc a,@a+dptr move code byte rela tive to dptr to accumulator 93 1 5 movc a,@a+pc move code byte rela tive to pc to accumulator 83 1 4 movx a,@ri move external ram (8-bit address) to a e2-e3 1 3* movx a,@dptr move external ram (16-bit address) to a e0 1 2* code inside rom/ram destination xram data 4* movx @ri,a move a to external ram (8-bit address) all other cases f2-f3 1 5* code inside rom/ram destination xram data 3* movx @dptr,a move a to external ram (16-bit address) all other cases f0 1 4* large 3 push direct push direct byte onto stack flat c0 2 3 large 2 pop direct pop direct byte from stack flat d0 2 2 xch a,rn exchange register with accumulator c8-cf 1 2 xch a,direct exchange direct byte with accumulator c5 2 3 xch a,@ri exchange indirect ram with accumulator c6-c7 1 3 xchd a,@ri exchange low-order nibble indirect ram with a d6-d7 1 3 table 6. data transfer * movx cycles depends on external data memory access time (ready pin)
DP80390 instructions set details - 11 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 2.2.5. p rogram branches mnemonic description code bytes cycles acall addr11 large 2 4 acall addr19 absolute subroutine call flat 0 x 11-0 x f1 3 5 lcall addr16 large 3 4 lcall addr24 long subroutine call flat 03 4 6 large 4 ret return from subroutine flat 22 1 5 large 4 reti return from interrupt flat 32 1 5 ajmp addr11 large 2 3 ajmp addr19 absolute jump flat 01-e1 3 4 ljmp addr16 large 3 4 ljmp addr24 long jump flat 02 4 5 sjmp rel short jump (relative address) 80 2 3 jmp @a+dptr jump indirect relative to the dptr 73 1 5 jz rel jump if accumulator is zero 60 2 4 jnz rel jump if accumulator is not zero 70 2 4 jc rel jump if carry flag is set 40 2 3 jnc rel jump if carry flag is not set 50 2 3 jb bit,rel jump if direct bit is set 20 3 5 jnb bit,rel jump if direct bit is not set 30 3 5 jbc bit,direct rel jump if direct bit is set and clear bit 10 3 5 cjne a,direct rel compare direct byte to a and jump if not equal b5 3 5 cjne a,#data rel compare immediate to a and jump if not equal b4 3 4 cjne rn,#data rel compare immediate to reg. and jump if not equal b8-bf 3 4 cjne @ri,#data rel compare immediate to ind. and jump if not equal b6-b7 3 5 djnz rn,rel decrement register and jump if not zero d8-df 2 4 djnz direct,rel decrement direct byte and jump if not zero d5 3 5 nop no operation 00 1 1 table 7. program branches
DP80390 instructions set details - 12 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 2.3. i nstruction set brief ? hexadecimal order opcode mnemonic opcode mnemonic 00 h nop 30 h jnb bit.rel 01 h ajmp addr11/addr19 31 h acall addr11/addr19 02 h ljmp addr16 /addr24 32 h reti 03 h rr a 33 h rlc a 04 h inc a 34 h addc a,#data 05 h inc direct 35 h addc a,direct 06 h inc @r0 36 h addc a,@r0 07 h inc @r1 37 h addc a,@r1 08 h inc r0 38 h addc a,r0 09 h inc r1 39 h addc a,r1 0a h inc r2 3a h addc a,r2 0b h inc r3 3b h addc a,r3 0c h inc r4 3c h addc a,r4 0d h inc r5 3d h addc a,r5 0e h inc r6 3e h addc a,r6 0f h inc r7 3f h addc a,r7 10 h jbc bit,rel 40 h jc rel 11 h acall addr11/addr19 41 h ajmp addr11/addr19 12 h lcall addr16/addr24 42 h orl direct,a 13 h rrc a 43 h orl direct,#data 14 h dec a 44 h orl a,#data 15 h dec direct 45 h orl a,direct 16 h dec @r0 46 h orl a,@r0 17 h dec @r1 47 h orl a,@r1 18 h dec r0 48 h orl a,r0 19 h dec r1 49 h orl a,r1 1a h dec r2 4a h orl a,r2 1b h dec r3 4b h orl a,r3 1c h dec r4 4c h orl a,r4 1d h dec r5 4d h orl a,r5 1e h dec r6 4e h orl a,r6 1f h dec r7 4f h orl a,r7 20 h jb bit.rel 50 h jnc rel 21 h ajmp addr11/addr19 51 h acall addr11/addr19 22 h ret 52 h anl direct,a 23 h rl a 53 h anl direct,#data 24 h add a,#data 54 h anl a,#data 25 h add a,direct 55 h anl a,direct 26 h add a,@r0 56 h anl a,@r0 27 h add a,@r1 57 h anl a,@r1 28 h add a,r0 58 h anl a,r0 29 h add a,r1 59 h anl a,r1 2a h add a,r2 5a h anl a,r2 2b h add a,r3 5b h anl a,r3 2c h add a,r4 5c h anl a,r4 2d h add a,r5 5d h anl a,r5 2e h add a,r6 5e h anl a,r6 2f h add a,r7 5f h anl a,r7
DP80390 instructions set details - 13 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. opcode mnemonic opcode mnemonic 60 h jz rel 90 h mov dptr,#data16 mov dptr,#data24 61 h ajmp addr11 91 h acall addr11 62 h xrl direct,a 92 h mov bit,c 63 h xrl direct,#data 93 h movc a,@a+dptr 64 h xrl a,#data 94 h subb a,#data 65 h xrl a,direct 95 h subb a,direct 66 h xrl a,@r0 96 h subb a,@r0 67 h xrl a,@r1 97 h subb a,@r1 68 h xrl a,r0 98 h subb a,r0 69 h xrl a,r1 99 h subb a,r1 6a h xrl a,r2 9a h subb a,r2 6b h xrl a,r3 9b h subb a,r3 6c h xrl a,r4 9c h subb a,r4 6d h xrl a,r5 9d h subb a,r5 6e h xrl a,r6 9e h subb a,r6 6f h xrl a,r7 9f h subb a,r7 70 h jnz rel a0 h orl c,bit 71 h acall addr11/addr19 a1 h ajmp addr11/addr19 72 h orl c,direct a2 h mov c,bit 73 h jmp @a+dptr a3 h inc dptr 74 h mov a,#data a4 h mul ab 75 h mov direct,#data a5 h - 76 h mov @r0,#data a6 h mov @r0,direct 77 h mov @r1,#data a7 h mov @r1,direct 78 h mov r0.#data a8 h mov r0,direct 79 h mov r1.#data a9 h mov r1,direct 7a h mov r2.#data aa h mov r2,direct 7b h mov r3.#data ab h mov r3,direct 7c h mov r4.#data ac h mov r4,direct 7d h mov r5.#data ad h mov r5,direct 7e h mov r6.#data ae h mov r6,direct 7f h mov r7.#data af h mov r7,direct 80 h sjmp rel b0 h anl c,bit 81 h ajmp addr11/addr19 b1 h acall addr11/addr19 82 h anl c,bit b2 h cpl bit 83 h movc a,@a+pc b3 h cpl c 84 h div ab b4 h cjne a,#data,rel 85 h mov direct,direct b5 h cjne a,direct,rel 86 h mov direct,@r0 b6 h cjne @r0,#data,rel 87 h mov direct,@r1 b7 h cjne @r1,#data,rel 88 h mov direct,r0 b8 h cjne r0,#data,rel 89 h mov direct,r1 b9 h cjne r1,#data,rel 8a h mov direct,r2 ba h cjne r2,#data,rel 8b h mov direct,r3 bb h cjne r3,#data,rel 8c h mov direct,r4 bc h cjne r4,#data,rel 8d h mov direct,r5 bd h cjne r5,#data,rel 8e h mov direct,r6 be h cjne r6,#data,rel 8f h mov direct,r7 bf h cjne r7,#data,rel
DP80390 instructions set details - 14 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. opcode mnemonic opcode mnemonic c0 h push direct e0 h movx a,@dptr c1 h ajmp addr11/addr19 e1 h ajmp addr11/addr19 c2 h clr bit e2 h movx a,@r0 c3 h clr c e3 h movx a,@r1 c4 h swap a e4 h clr a c5 h xch a, direct e5 h mov a, direct c6 h xch a,@r0 e6 h mov a,@r0 c7 h xch a,@r1 e7 h mov a,@r1 c8 h xch a,r0 e8 h mov a,r0 c9 h xch a,r1 e9 h mov a,r1 ca h xch a,r2 ea h mov a,r2 cb h xch a,r3 eb h mov a,r3 cc h xch a,r4 ec h mov a,r4 cd h xch a,r5 ed h mov a,r5 ce h xch a,r6 ee h mov a,r6 cf h xch a,r7 ef h mov a,r7 d0 h pop direct f0 h movx @dptr,a d1 h acall addr11/addr19 f1 h acall addr11/addr19 d2 h setb bit f2 h movx @r0,a d3 h setb c f3 h movx @r1,a d4 h da a f4 h cpl a d5 h djnz direct, rel f5 h mov direct, a d6 h xchd a,@r0 f6 h mov @r0,a d7 h xchd a,@r1 f7 h mov @r1,a d8 h djnz r0,rel f8 h mov r0,a d9 h djnz r1,rel f9 h mov r1,a da h djnz r2,rel fa h mov r2,a db h djnz r3,rel fb h mov r3,a dc h djnz r4,rel fc h mov r4,a dd h djnz r5,rel fd h mov r5,a de h djnz r6,rel fe h mov r6,a df h djnz r7,rel ff h mov r7,a table 8. instruction set br ief in hexadecimal order
DP80390 instructions set details - 15 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3. i nstructions set details 3.1. acall * 3.1.1. large instruction: acall addr11 function: absolute call description: acall unconditionally calls a s ubroutine located at the indicated address. the instruction increments t he pc twice to obt ain the address of the following instruct ion, then pushes the 16-bit result onto the stack (low-order byte first) and increm ents the stack pointer twice. the destination address is obtained by su ccessively concatenating the five high-order bits of the in cremented pc, opcode bits 7-5, the second byte of the instruction. the subroutine ca lled must therefore start within the same 2k block of program memory as the first byte of the instruction following acall. no flags are affected. operation: (pc) (pc) + 2 (sp) (sp) + 1 ((sp)) (pc7-0) (sp) (sp) + 1 ((sp)) (pc15-8) (pc10-0) page address bytes : 2 cycles : 4 encoding: a10 a9 a8 1 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0
DP80390 instructions set details - 16 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.1.2. flat instruction: acall addr19 function: absolute call description: acall unconditionally calls a s ubroutine located at the indicated address. the instruction increments the pc triple to obtain the address of the following instruct ion, then pushes the 24-bit result onto the stack (low-order byte first) and increm ents the stack pointer triple. the destination address is obtained by su ccessively concatenating the five high-order bits of the incremented pc, opcode bits 7-5, the second and third byte of the instruction. the subroutine called must therefore start within the same 512k block of program memory as the first byte of the instruction following acall. no flags are affected. operation: (pc) (pc) + 3 (sp) (sp) + 1 ((sp)) (pc7-0) (sp) (sp) + 1 ((sp)) (pc15-8) (sp) (sp) + 1 ((sp)) (pc23-16) (pc18-0) page address bytes : 3 cycles : 5 encoding: a18 a17 a16 1 0 0 0 1 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 * instruction modified regarding to standard 80c51
DP80390 instructions set details - 17 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.2. add instruction: add a, function : adds a to the source operand and returns the result to a. description: add adds the byte variable indicat ed to the accumulator, leaving the result in the accumulator. the carry and auxiliary carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise. when adding unsigned integer s, the carry flag indicates an overflow occurred. ov is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise ov is cleared. when adding signed integers, ov indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands. four source operand addressing modes are allowed: register, direct, regi ster- indirect, or immediate. 3.2.1. add a, r n operation: (pc) (pc) + 1 (a) (a) + (rn) bytes: 1 cycles: 1 encoding: 0 0 1 0 1 r r r 3.2.2. add a, direct operation : (pc) (pc) + 2 (a) (a) + (direct) bytes: 2 cycles: 2 encoding: 0 0 1 0 0 1 0 1 direct address
DP80390 instructions set details - 18 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.2.3. add a, @r i operation : (pc) (pc) + 1 (a) (a) + ((ri)) bytes: 1 cycles: 2 encoding: 0 0 1 0 0 1 1 i 3.2.4. add a, # data operation: (pc) (pc) + 2 (a) (a) + #data bytes: 2 cycles: 2 encoding: 0 0 1 0 0 1 0 0 immediate data
DP80390 instructions set details - 19 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.3. addc instruction: addc a, < src-byte> function: adds a and the sour ce operand, then adds one (1) if cy is set, and puts the result in a. description: addc simultaneously adds the byte variable indicated, the carry flag and the accumulator contents, leaving the result in the accumulator. the carry and auxiliary carry flags ar e set, respectively, if there is a carry out of bit 7 or bit 3, and cl eared otherwise. when adding unsigned integers, the carry flag indicates an ov erflow occurred. ov is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise ov is clear ed. when adding signed integers, ov indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands. four source operand-addressing modes ar e allowed: register= direct, register- indirect, or immediate. 3.3.1. addc a, r n operation: (pc) (pc) + 1 (a) (a) + (c) + (rn) bytes: 1 cycles: 1 encoding: 0 0 1 1 1 r r r 3.3.2. addc a, direct operation: (pc) (pc) + 2 (a) (a) + (c) + (direct) bytes: 2 cycles: 2 encoding: 0 0 1 1 0 1 0 1 direct address
DP80390 instructions set details - 20 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.3.3. addc a, @r i operation: (pc) (pc) + 1 (a) (a) + (c) + ((ri)) bytes: 1 cycles: 2 encoding: 0 0 1 1 0 1 1 i 3.3.4. addc a, # data operation: (pc) (pc) + 2 (a) (a) + (c) + #data bytes: 2 cycles: 2 encoding: 0 0 1 1 0 1 0 0 immediate data
DP80390 instructions set details - 21 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.4. ajmp * 3.4.1. large instruction: ajmp addr11 function: absolute jump description: ajmp transfers program execution to the indicated address, which is formed at runtime by concatenating t he high-order five bits of the pc ( after incrementing the pc twice), opcode bits 7-5, the second byte of the instruction. the destination must therefore be wit hin the same 2k block of program memory as the firs t byte of the instruction following ajmp. operation: (pc) (pc) + 2 (pc10-0) page address bytes: 2 cycles: 3 encoding: a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0
DP80390 instructions set details - 22 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.4.2. flat instruction: ajmp addr19 function: absolute jump description: ajmp transfers program execution to the indicated address, which is formed at runtime by concatenating t he high-order five bits of the pc ( after incrementing the pc triple), opcode bits 7-5, the second and the third byte of the instruction. the des tination must therefore be within the same 512k block of program memory as the first byte of the instruction following ajmp. operation: (pc) (pc) + 3 (pc18-0) page address bytes: 3 cycles: 4 encoding: a18 a17 a16 0 0 0 0 1 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 * instruction modified regarding to standard 80c51
DP80390 instructions set details - 23 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.5. anl instruction: anl , function: logical and for byte operands description: anl performs the bit wise logical and operation between the variables indicated and stores the results in the destination variable. no flags are affected (except p, if = a). the two operands allow six addressing mode combinations. when t he destination is a accumulator, the source can use register, direc t, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the accumulator or immediate data. note: when this instruction is used to m odify an output port, the value used as the original port data will be read from the output dat a latch, not the input pins. 3.5.1. anl a, r n operation: (pc) (pc) + 1 (a) (a) and (rn) bytes: 1 cycles: 1 encoding: 0 1 0 1 1 r r r 3.5.2. anl a, direct operation: (pc) (pc) + 2 (a) (a) and (direct) bytes: 2 cycles: 2 encoding: 0 1 0 1 0 1 0 1 direct address
DP80390 instructions set details - 24 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.5.3. anl a, @r i operation: (pc) (pc) + 1 (a) (a) and ((ri)) bytes: 1 cycles: 2 encoding: 0 1 0 1 0 1 1 i 3.5.4. anl a, # data operation : (pc) (pc) + 2 (a) (a) and #data bytes: 2 cycles: 2 encoding: 0 1 0 1 0 1 0 0 immediate data 3.5.5. anl direct , a operation: (pc) (pc) + 2 (direct) (direct) and (a) bytes: 2 cycles: 3 encoding: 0 1 0 1 0 0 1 0 direct address 3.5.6. anl direct , # data operation: (pc) (pc) + 3 (direct) (direct) and #data bytes: 3 cycles: 3 encoding: 0 1 0 1 0 0 1 1 direct address immediate data instruction: anl c,
DP80390 instructions set details - 25 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. function: logical and for bit operands description: if the boolean value of the source bit is a logic 0 then clear the carry flag; otherwise leave the carry flag in its current state. a slash (?/? preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected . no other flags are affected. only direct bit addressing is allowed for the source operand. 3.5.7. anl c, bit operation: (pc) (pc) + 2 (c) (c) and (bit) bytes: 2 cycles: 2 encoding: 1 0 0 0 0 0 1 0 bit address 3.5.8. anl c, / bit operation: (pc) (pc) + 2 (c) (c) and / (bit) bytes: 2 cycles: 2 encoding: 1 0 1 1 0 0 0 0 bit address
DP80390 instructions set details - 26 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.6. cjne instruction: cjne , < src-byte >, rel function: compare and jump if not equal. description: cjne compares the magnitudes of the first two operands, and branches if their values are not equal. the branch destination is computed by adding the signed relati ve displacement in the last instruction byte to the pc, after incr ementing the pc to the start of the next instruction. the carry flag is se t if the unsigned integer value of is less than the unsigne d integer value of ; otherwise, the carry is cleared. neit her operand is affected. the first two operands allow four addre ssing mode combinations: the accumulator may be compared with any directly addr essed byte or immediate data, and any indirect ram location or work ing register can be compared with an immediate constant. 3.6.1. cjne a, direct , rel operation: (pc) (pc) + 3 if (a) < > (direct) then (pc) (pc) + relative offset if (a) < (direct) then (c) 1 else (c) 0 bytes: 3 cycles: 5 encoding: 1 0 1 1 0 1 0 1 direct address relative address
DP80390 instructions set details - 27 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.6.2. cjne a, # data , rel operation: (pc) (pc) + 3 if (a) < > data then (pc) (pc) + relative offset if (a) < data then (c) 1 else (c) 0 bytes: 3 cycles: 4 encoding: 1 0 1 1 0 1 0 0 immediate data relative address 3.6.3. cjne rn, # data , rel operation: (pc) (pc) + 3 if (rn) < > data then (pc) (pc) + relative offset if (rn) < data then (c) 1 else (c) 0 bytes: 3 cycles: 4 encoding: 1 0 1 1 1 r r r immediate data relative address
DP80390 instructions set details - 28 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.6.4. cjne @r i , # data , rel operation: (pc) (pc) + 3 if ((ri)) < > data then (pc) (pc) + relative offset if ((ri)) < data then (c) 1 else (c) 0 bytes: 3 cycles: 5 encoding: 1 0 1 1 0 1 1 i immediate data relative address
DP80390 instructions set details - 29 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.7. clr 3.7.1. clr a function: clear accumulator description: the accumulator is cleared (all bits se t to zero). no flags are affected. operation: (pc) (pc) + 1 (a) 0 bytes: 1 cycles: 1 encoding: 1 1 1 0 0 1 0 0 3.7.2. clr bit function: clear bit description: the indicated bit is cleared (reset to ze ro). no other flags are affected. operation: (pc) (pc) + 2 bit 0 bytes: 2 cycles: 3 encoding: 1 1 0 0 0 0 1 0 bit address
DP80390 instructions set details - 30 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.7.3. clr c function: clear carry description: the carry flag is cleared (reset to zero). no other flags are affected. operation: (pc) (pc) + 1 (c) 0 bytes: 1 cycles: 1 encoding: 1 1 0 0 0 0 1 1
DP80390 instructions set details - 31 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.8. cpl 3.8.1. cpl a function: complement accumulator description: each bit of the accumulator is logically complemented (one?s complement). bits which previous ly contained a one are changed to zero and vice versa. no flags are affected. operation: (pc) (pc) + 1 (a) / (a) bytes: 1 cycles: 1 encoding: 1 1 1 1 0 1 0 0 3.8.2. cpl bit function: complement bit description: the bit variable specified is co mplemented. a bit which had been a one is changed to zero and vice versa. no other flags are affected. cpl can operate on the carry or any directly addressable bit. note: when this instruction is used to modi fy an output pin, the value used as the original data will be r ead from the output data latch, not the input pin. operation: (pc) (pc) + 2 (c) (bit) bytes: 2 cycles: 3 encoding: 1 0 1 1 0 0 1 0 bit address
DP80390 instructions set details - 32 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.8.3. cpl c function: complement carry description: the carry flag is complemented. a bit which had been a one is changed to zero and vice versa. operation : (pc) (pc) + 1 (c) / (c) bytes: 1 cycles: 1 encoding: 1 0 1 1 0 0 1 1
DP80390 instructions set details - 33 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.9. da instruction: da a function: decimal adjust a ccumulator for addition description: da a adjusts the eight-bit value in the accumulator resulting from the earlier addition of two variable s (each in packed bcd format), producing two four-bit digits. any add or addc instruction may have been used to perform the addition. if accumulator bits 3-0 are greater than nine (xxxx1010-xxxx1111), or if the ac flag is one, six is added to the accumulator producing the proper bc d digit in the low- order nibble. this internal addition would set the ca rry flag if a carry-out of the low- order four-bit field propagated through all high-order bits , but it would not clear the carry flag otherwise. if the carry flag is now set, or if the four high-order bits now exceed nine (1010xxxx-1111xxxx), these high-order bits are incremented by six, producing the proper bcd digit in the high-order nibble. again, this would set the carry flag if there was a carry-out of the high-order bits, but wouldn't clear the carry. the carry flag thus indicates if the sum of the original two bcd va riables is greater than 100, allowing multiple precision decimal addition. ov is not affected. all of this occurs during the one instruction cycle. essentially; this instruction performs the decimal conver sion by adding 00 h , 06 h , 60 h , or 66 h to the accumulator, depending on initial accumulator and psw conditions. note: da a cannot simply convert a hexadecimal number in the accumulator to bcd notation, nor does da a apply to decimal subtraction. operation: (pc) (pc) + 1 if [[(a3-0) > 9] ^ [(ac) = 1]] then (a3-0) (a3-0) + 6 next if [[(a7-4) > 9] ^ [(c) = 1]] then (a7-4) (a7-4) + 6 bytes: 1 cycles: 3 encoding: 1 1 0 1 0 1 0 0
DP80390 instructions set details - 34 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.10. dec instruction: dec byte function: decrement byte description: the variable indicated is decremented by 1. an original value of 00 h will underflow to 0 ff h. no flags are affected. four operand addressing modes are allowed: accumu lator, register, direc t, or register-indirect. note: when this instruction is used to m odify an output port, the value used as the original port data will be read from the output data latch, not the input pins. 3.10.1. dec a operation: (pc) (pc) + 1 (a) (a) - 1 bytes: 1 cycles: 1 encoding: 0 0 0 1 0 1 0 0 3.10.2. dec r n operation: (pc) (pc) + 1 (rn) (rn) - 1 bytes: 1 cycles: 2 encoding: 0 0 0 1 1 r r r
DP80390 instructions set details - 35 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.10.3. dec direct operation: (pc) (pc) + 2 (direct) (direct) - 1 bytes: 2 cycles: 3 encoding: 0 0 0 1 0 1 0 1 direct address 3.10.4. dec @r i operation: (pc) (pc) + 1 ((ri)) ((ri)) - 1 bytes: 1 cycles: 3 encoding: 0 0 0 1 0 1 1 i
DP80390 instructions set details - 36 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.11. div instruction: div ab function: divide description: div ab divides the unsigned eight-bi t integer in the accumulator by the unsigned eight-bit integer in register b. the accumulator receives the integer part of the quotient; register b receives the integer remainder. the carry and ov flags will be cleared. exception: if b had originally contained 00 h, the values returned in the accumulator and b register will be undef ined and the overflow flag will be set. the carry flag is cleared in any case. operation: (pc) (pc) + 1 (a15-8) (a) / (b) ? result?s bits 15..8 (b7-0) (a) / (b) ? result?s bits 7..0 bytes: 1 cycles: 6 encoding: 1 0 0 0 0 1 0 0
DP80390 instructions set details - 37 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.12. djnz instruction: djnz , function: decrement and jump if not zero description: djnz decrements the location i ndicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. an original value of 00 h wil l underflow to 0ff h. no flags are affected. the branch destination woul d be computed by adding the signed relative-displacement value in t he last instruction byte to the pc, after incrementing the pc to the firs t byte of the follo wing instruction. the location decremented may be a r egister or directly addressed byte. note: when this instruction is used to modi fy an output port, the value used as the original port data will be read from the output dat a latch, not the input pins. 3.12.1. djnz r n , rel operation: (pc) (pc) + 2 (rn) (rn) - 1 if (rn) 0 then (pc) (pc) + rel bytes: 2 cycles: 4 encoding: 1 1 0 1 1 r r r relative address
DP80390 instructions set details - 38 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.12.2. djnz direct , rel operation: (pc) (pc) + 3 (direct) (direct) - 1 if (direct) 0 then (pc) (pc) + rel bytes: 3 cycles: 5 encoding: 1 1 0 1 0 1 0 1 direct address relative address
DP80390 instructions set details - 39 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.13. inc instruction: inc operand function: increment description: inc increments the indi cated variable by 1. an original value of 0ffh will overflow to 00h. no flags ar e affected. three addressing modes are allowed: register, direc t, or register-indirect. note: when this instruction is used to modi fy an output port, the value used as the original port data will be read from the output data latch, not the input pins. 3.13.1. inc a operation: (pc) (pc) + 1 (a) (a) + 1 bytes: 1 cycles: 1 encoding: 0 0 0 0 0 1 0 0 3.13.2. inc r n operation: (pc) (pc) + 1 (rn) (rn) + 1 bytes: 1 cycles: 2 encoding: 0 0 0 0 1 r r r
DP80390 instructions set details - 40 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.13.3. inc direct operation: (pc) (pc) + 2 (direct) (direct) + 1 bytes: 2 cycles: 3 encoding: 0 0 0 0 0 1 0 1 direct address 3.13.4. inc @r i operation: (pc) (pc) + 1 ((ri)) ((ri)) + 1 bytes: 1 cycles: 3 encoding: 0 0 0 0 0 1 1 i 3.13.5. inc dptr* function: increment active data pointer description: increment the 16-bit dat a pointer (in large) or 24-bit data pointer (in flat) by 1. a 16-bit/24-bit increment (modulo 2 16 /2 24 ) is performed; an overflow of the low-order byte of the data pointer (dpl ) from 0xff to 0x00 will increment the high-order by te (dph). no flags are affected. this is the only 16-bit/24-bit regist er which can be incremented or decremented. refer to data poin ter extended registers chapter of DP80390 specification. operation: (pc) (pc) + 1 (dptr) (dptr) + 1 bytes: 1 cycles: 1 encoding: 1 0 1 0 0 0 1 1
DP80390 instructions set details - 41 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.14. jb instruction: jb bit, rel function: jump if bit is set description: if the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruction. t he branch destination is computed by adding the signed relative-displacem ent in the third instruction byte to the pc, after incrementing the pc to the first byte of the next instruction. the bit tested is not modified. no flags are affected. operation: (pc) (pc) + 3 if (bit) = 1 then (pc) (pc) + rel bytes: 3 cycles: 5 encoding: 0 0 1 0 0 0 0 0 bit address relative address
DP80390 instructions set details - 42 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.15. jbc instruction: jbc bit, rel function: jump if bit is set and clear bit description: if the indicated bit is one, branch to the address indicated; otherwise proceed with the next instruction. in either case, clear the designated bit. the branch destination is computed by adding the signed relative displacement in the third instruction byte to the pc, after incrementing the pc to the first byte of the next instruction. no flags are affected. note: when this instruction is used to test an output pin, the value used as the original data will be read from the output data latc h, not the input pin. operation: (pc) (pc) + 3 if (bit) = 1 then (bit) 0 (pc) (pc) + rel bytes: 3 cycles: 5 encoding: 0 0 0 1 0 0 0 0 bit address relative address
DP80390 instructions set details - 43 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.16. jc instruction: jc rel function: jump if carry is set description: if the carry flag is set, branch to the address indicated; otherwise proceed with the next instruction. t he branch destination is computed by adding the signed relative- displa cement in the second instruction byte to the pc, after incrementing t he pc twice. no flags are affected. operation: (pc) (pc) + 2 if (c) = 1 then (pc) (pc) + rel bytes: 2 cycles: 3 encoding: 0 1 0 0 0 0 0 0 relative address
DP80390 instructions set details - 44 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.17. jmp* instruction: jmp @a + dptr function: jump indirect description: add the eight-bit unsigned contents of the accumulator with the 16-bit (in large)/24-bit (in flat) active data pointer, and load the resulting sum to the program counter. this will be the address for subsequent instruction fetches. 16-bit/24-bit additi on is performed: a carry-out from the low-order eight bits propagates through the higher-order bits. neither the accumulator nor the data pointer is altered. no flags are affected. operation: (pc) (a) + (dptr) bytes: 1 cycles: 5 encoding: 0 1 1 1 0 0 1 1
DP80390 instructions set details - 45 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.18. jnb instruction: jnb bit,rel function: jump if bit is not set description: if the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next instruction. t he branch destination is computed by adding the signed relative-displacem ent in the third instruction byte to the pc, after incrementing the pc to the first byte of the next instruction. the bit tested is not modified. no flags are affected. operation: (pc) (pc) + 3 if (bit) = 0 then (pc) (pc) + rel. bytes: 3 cycles: 5 encoding: 0 0 1 1 0 0 0 0 bit address relative address
DP80390 instructions set details - 46 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.19. jnc instruction: jnc rel function: jump if carry is not set description: if the carry flag is a zero, branch to the address indicated; otherwise proceed with the next instruction. t he branch destination is computed by adding the signed relative-displ acement in the second instruction byte to the pc, after incrementing t he pc twice to point to the next instruction. the carry flag is not modified. operation: (pc) (pc) + 2 if (c) = 0 then (pc) (pc) + rel bytes: 2 cycles: 3 encoding: 0 1 0 1 0 0 0 0 relative address
DP80390 instructions set details - 47 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.20. jnz instruction: jnz rel function: jump if accumulator is not zero description: if any bit of the accumulator is a one, branch to the indicated address; otherwise proceed with the next instru ction. the branch destination is computed by adding the signed relati ve-displacement in the second instruction byte to the pc, afte r incrementing the pc twice. the accumulator is not modified. no flags are affected. operation: (pc) (pc) + 2 if (a) 0 then (pc) (pc) + rel. bytes: 2 cycles: 4 encoding: 0 1 1 1 0 0 0 0 relative address
DP80390 instructions set details - 48 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.21. jz instruction: jz rel function: jump if accumulator is zero description: if all bits of the accumulator are zero, branch to the address indicated; otherwise proceed with the next instru ction. the branch destination is computed by adding the signed relati ve-displacement in the second instruction byte to the pc, afte r incrementing the pc twice. the accumulator is not modified. no flags are affected. operation: (pc) (pc) + 2 if (a) = 0 then (pc) (pc) + rel bytes: 2 cycles: 4 encoding: 0 1 1 0 0 0 0 0 relative address
DP80390 instructions set details - 49 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.22. lcall * 3.22.1. large instruction: lcall addr16 function: long call description: lcall calls a subroutine locat ed at the indicated address. the instruction adds three to the prog ram counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the st ack pointer by two. the high-order and low-order bytes of t he pc are then loaded, respectively, with the second and third bytes of the lcal l instruction. program execution continues with the instruction at this address. the subroutine may therefore begin anywhere in the fu ll 64 kb program memory address space. no flags are affected. operation: (pc) (pc) + 3 (sp) (sp) + 1 ((sp)) (pc7-0) (sp) (sp) + 1 ((sp)) (pc15-8) (pc) addr15-0 bytes: 3 cycles: 4 encoding: 0 0 0 1 0 0 1 0 address 15..8 address 7..0
DP80390 instructions set details - 50 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.22.2. flat instruction: lcall addr24 function: long call description: lcall calls a subroutine locat ed at the indicated address. the instruction adds four to the program counter to generate the address of the next instruction and t hen pushes the 24-bit result onto the stack (low byte first), incrementing the stack poi nter by three. the high-order and low-order bytes of the pc are t hen loaded, respectively, with the second, third and fourth bytes of the lcall instruction. program execution continues with the instruct ion at this address. the subroutine may therefore begin anywhere in th e full 16 mb program memory address space. no flags are affected. operation: (pc) (pc) + 4 (sp) (sp) + 1 ((sp)) (pc7-0) (sp) (sp) + 1 ((sp)) (pc15-8) (sp) (sp) + 1 ((sp)) (pc23-16) (pc) addr23-0 bytes: 4 cycles: 6 encoding: 0 0 0 1 0 0 1 0 address 23..16 address 15..8 address 7..0 * instruction modified regarding to standard 80c51
DP80390 instructions set details - 51 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.23. ljmp * 3.23.1. large instruction: ljmp addr16 function: long jump description: ljmp causes an unconditional br anch to the indicated address, by loading the pc with the second and third instruction bytes. the destination may therefore be anyw here in the full 64 kb program memory address space. no flags are affected. operation: (pc) addr15... addr0 bytes: 3 cycles: 4 encoding: 0 0 0 0 0 0 1 0 address 15..8 address 7..0 3.23.2. flat instruction: lcall addr24 function: long jump description: ljmp causes an unconditional br anch to the indicated address, by loading the pc with the second, thir d and fourth instruction bytes. the destination may therefore be anyw here in the full 16mb program memory address space. no flags are affected. operation: (pc) addr23... addr0 bytes: 4 cycles: 6 encoding: 0 0 0 0 0 0 1 0 address 23..16 address 15..8 address 7..0 * instruction modified regarding to standard 80c51
DP80390 instructions set details - 52 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.24. mov instruction: mov , function: move byte variable description: the byte variable indicated by t he second operand is copied into the location specified by the first operand. the source byte is not affected. no other register or flag is affected. this is by far the most flexible operation. fifteen combinat ions of source and destination addressing modes are allowed. 3.24.1. mov a, r n operation: (pc) (pc) + 1 (a) (rn) bytes: 1 cycles: 1 encoding: 1 1 1 0 1 r r r 3.24.2. mov a, direct operation: (pc) (pc) + 2 (a) (direct) note: mov a, acc is a valid instruction. bytes: 2 cycles: 2 encoding: 1 1 1 0 0 1 0 1 direct address 3.24.3. mov a, @r i operation: (pc) (pc) + 1
DP80390 instructions set details - 53 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. (a) ((ri)) bytes: 1 cycles: 2 encoding: 1 1 1 0 0 1 1 i 3.24.4. mov a, # data operation: (pc) (pc) + 2 (a) #data bytes: 2 cycles: 2 encoding: 0 1 1 1 0 1 0 0 immediate data 3.24.5. mov r n , a operation: (pc) (pc) + 1 (rn) (a) bytes: 1 cycles: 1 encoding: 1 1 1 1 1 r r r 3.24.6. mov r n , direct operation: (pc) (pc) + 2 (rn) (direct) bytes: 2 cycles: 3 encoding: 1 0 1 0 1 r r r direct address 3.24.7. mov r n , # data operation: (pc) (pc) + 2 (rn) #data
DP80390 instructions set details - 54 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. bytes: 2 cycles: 2 encoding: 0 1 1 1 1 r r r immediate data 3.24.8. mov direct , a operation: (pc) (pc) + 2 (direct) (a) bytes: 2 cycles: 2 encoding: 1 1 1 1 0 1 0 1 direct address 3.24.9. mov direct , r n operation: (pc) (pc) + 2 (direct) (rn) bytes: 2 cycles: 2 encoding: 1 0 0 0 1 r r r direct address 3.24.10. mov direct , direct operation: (pc) (pc) + 3 (direct) (direct) bytes: 3 cycles: 3 encoding: 1 0 0 0 0 1 0 1 direct address (source) direct address (destination) 3.24.11. mov direct , @r i operation: (pc) (pc) + 2 (direct) ((ri))
DP80390 instructions set details - 55 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. bytes: 2 cycles: 3 encoding: 1 0 0 0 0 1 1 i direct address 3.24.12. mov direct , # data operation: (pc) (pc) + 2 (direct) #data bytes: 3 cycles: 3 encoding: 0 1 1 1 0 1 0 1 direct address (source) immediate data 3.24.13. mov @r i , a operation: (pc) (pc) + 1 ((ri)) (a) bytes: 1 cycles: 2 encoding: 1 1 1 1 0 1 1 i 3.24.14. mov @r i , direct operation: (pc) (pc) + 2 ((ri)) (direct) bytes: 2 cycles: 3 encoding: 1 0 1 0 0 1 1 i direct address 3.24.15. mov @r i , # data operation: (pc) (pc) + 2 ((ri)) #data bytes: 2
DP80390 instructions set details - 56 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. cycles: 2 encoding: 0 1 1 1 0 1 1 i immediate data 3.24.16. mov c, bit function: move bit data description: the boolean variable indicat ed by the second operand (directly addressable bit) is copied into carry flag. no other register or flag is affected. operation: (pc) (pc) + 2 (c) (bit) bytes: 2 cycles: 2 encoding: 1 0 1 0 0 0 1 0 bit address 3.24.17. mov bit , c function: move carry flag description: the carry flag is copied into the b oolean variable indicated by the first operand (directly addressable bit). no other register or flag is affected. operation: (pc) (pc) + 2 (bit) (c) bytes: 2 cycles: 3 encoding: 1 0 0 1 0 0 1 0 bit address
DP80390 instructions set details - 57 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.24.18. mov dptr, # data 16 - large function: load active data pointer with a 16-bit constant in large mode description: the active data pointer is loaded with the 16 -bit constant indicated. the 16-bit constant is loaded into t he second and third bytes of the instruction. the second byte (dph) is the high-order byte, while the third byte (dpl) holds the low-order by te. no flags are a ffected. this is the only instruction which moves 16 bits of data at once. operation: (pc) (pc) + 3 dph immediate data15...8 dpl immediate data7..0 bytes: 3 cycles: 3 encoding: 1 0 0 0 0 1 0 1 immediate data 15...8 immediate data 7...0 3.24.19. mov dptr, # data 24* - flat function: load active data pointer with a 24-bit constant in flat mode description: the active data pointer is loaded with the 24 -bit constant indicated. the 24 bit constant is loaded into the se cond, third and fourth bytes of the instruction. the second byte (dpx or dpx1) is the high-order byte, while the third byte (dph) holds t he mid-order byte and fourth (dpl). no flags are affected. this is the only instruction which moves 24 bits of data at once. operation: (pc) (pc) + 4 dpx/dpx1 immediate data23...16 dph immediate data15...8 dpl immediate data7..0 bytes: 4 cycles: 4 encoding: 1 0 0 0 0 1 0 1 immediate data 23...16 immediate data 15...8 immediate data 7...0 * instruction modified regarding to standard 80c51
DP80390 instructions set details - 58 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.25. movc* instruction: movc a, @a + function: move code byte description: the movc instructions load the accumulator with a code byte, or constant from program memory. the address of the byte fetched is the sum of the original unsigned eight-bit accu mulator contents and the contents of a 16-bit/24-bit base regist er, which may be either the data pointer or the pc. in the latter ca se, the pc is incremented to the address of the following instruction before being added to the accumulator; otherwise the base regist er is not altered. 16-bit/24-bit addition is performed so a carry-out from the low-order eight bits may propagate through higher-order bi ts. no flags are affected. 3.25.1. movc a, @a + dptr operation: (pc) (pc) + 1 (a) ((a) + (dptr)) bytes: 1 cycles: 5 encoding: 1 0 0 1 0 0 1 1 3.25.2. movc a, @a + pc operation: (pc) (pc) + 1 (a) ((a) + (pc)) bytes: 1 cycles: 4 encoding: 1 0 0 0 0 0 1 1 * different registers are used in flat and large mode
DP80390 instructions set details - 59 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.26. movx* instruction: movx , function: move external description: the movx instructions transfer data between the accumulator and a byte of external data memory, hence the x appended to mov. there are two types of instructions, differing in whether they pr ovide an 8-bit in both modes or 16-bit in large/24-bit in flat indirect address to the external data ram. in the first type, the c ontents of r0 or r1 in the current register bank provides an eight-bit address, in t he second type of movx instructions, the active data pointer generat es 16-bit/24-bit address. 3.26.1. movx a, @r i operation: (pc) (pc) + 1 (a) ((ri)) bytes: 1 cycles: 3* encoding: 1 1 1 0 0 0 1 i 3.26.2. movx a, @dptr operation: (pc) (pc) + 1 (a) ((dptr)) bytes: 1 cycles: 2* encoding: 1 1 1 0 0 0 0 0
DP80390 instructions set details - 60 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.26.3. movx @r i , a operation: (pc) (pc) + 1 ((ri)) (a) bytes: 1 cycles: 4* ? if movx code is executed from on-chip rom or on-chip ram, and destination data are placed inside off-chip xram 5* ? for all other cases as follow: code inside off-chip xprg, desti nation inside off-chip xram code inside off-chip xprg, des tination inside off-chip xprg code inside off-chip xprg, destination inside on-chip prg ram code inside on-chip rom, desti nation inside off-chip xprg code inside on-chip rom, desti nation inside on-chip prg ram code inside on-chip ram, desti nation inside off-chip xprg code inside on-chip ram, desti nation inside on-chip prg ram encoding: 1 1 1 1 0 0 1 i 3.26.4. movx @dptr, a operation: (pc) (pc) + 1 ((dptr)) (a) bytes: 1 cycles: 3* ? if movx code is executed from on-chip rom or on-chip ram, and destination data are placed inside off-chip xram 4* ? for all other cases as listed above encoding: 1 1 1 1 0 0 0 0 * movx cycles depends on ready pin. shown values with 0 wait-states.
DP80390 instructions set details - 61 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.27. mul instruction: mul ab function: multiply description: mul ab multiplies t he unsigned eight-bit int egers in the accumulator and register b. the low-order byte of the sixteen-bit product is left in the accumulator, and the high-order byte in b. if the product is greater than 255 (0ff h) the overflow flag is set; otherwise it is cleared. the carry flag is always cleared. operation: (pc) (pc) + 1 (a) (a) x (b) ? result?s bits 7..0 (b) (a) x (b) ? result?s bits 15..8 bytes: 1 cycles: 2 encoding: 1 0 1 0 0 1 0 0
DP80390 instructions set details - 62 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.28. nop function: no operation description: execution continues at the following instruction. other than the pc, no registers or flags are affected. operation: (pc) (pc) + 1 bytes: 1 cycles: 1 encoding: 0 0 0 0 0 0 0 0
DP80390 instructions set details - 63 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.29. orl instruction: orl , function: logical or for byte variables description: orl performs the bit wise logical or operation between the indicated variables, storing the results in the destination byte. no flags are affected (except p, if = a). the two operands allow six addre ssing mode combinations. when the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addr essing; when the destination is a direct address, the source can be t he accumulator or immediate data. note: when this instruction is used to modi fy an output port, the value used as the original port data will be read from the output data latch, not the input pins. 3.29.1. orl a, r n operation: (pc) (pc) + 1 (a) (a) or (rn) bytes: 1 cycles: 1 encoding: 0 1 0 0 1 r r r 3.29.2. orl a, direct operation: (pc) (pc) + 2 (a) (a) or (direct) bytes: 2 cycles: 2 encoding: 0 1 0 0 0 1 0 1 direct address
DP80390 instructions set details - 64 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.29.3. orl a, @r i operation: (pc) (pc) + 1 (a) (a) or ((ri)) bytes: 1 cycles: 2 encoding: 0 1 0 0 0 1 1 i 3.29.4. orl a, # data operation: (pc) (pc) + 1 (a) (a) or #data bytes: 2 cycles: 2 encoding: 0 1 0 0 0 1 0 0 immediate data 3.29.5. orl direct , a operation: (pc) (pc) + 1 (direct) (direct) or (a) bytes: 2 cycles: 3 encoding: 0 1 0 0 0 0 1 0 direct address 3.29.6. orl direct , # data operation: (pc) (pc) + 1 (direct) (direct) or #data bytes: 3 cycles: 3 encoding: 0 1 0 0 0 0 1 1 direct address immediate data instruction: orl c,
DP80390 instructions set details - 65 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. function: logical or for bit variables description: set the carry flag if the boolean value is a logic 1; leave the carry in its current state otherwise. a slash (?/?) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source valu e, but the source bit itself is not affected. no other flags are affected. 3.29.7. orl c, bit operation: (pc) (pc) + 2 (c) (c) or (bit) bytes: 2 cycles: 2 encoding: 0 1 1 1 0 0 1 0 bit address 3.29.8. orl c, / bit operation: (pc) (pc) + 2 (c) (c) or /(bit) bytes: 2 cycles: 2 encoding: 1 0 1 0 0 0 0 0 bit address
DP80390 instructions set details - 66 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.30. pop* 3.30.1. large instruction: pop direct function: pop from stack description: the contents of the internal ra m location addressed by the stack pointer are read, and t he stack pointer is decremented by one. the value read is the transfer to the di rectly addressed byte indicated. no flags are affected. operation: (pc) (pc) + 2 (direct) ((sp)) (sp) (sp) - 1 bytes: 2 cycles: 2 encoding: 1 1 0 1 0 0 0 0 direct address 3.30.2. flat instruction: pop direct function: pop from stack description: the contents of the internal ra m location addressed by the stack pointer are read, and t he stack pointer is decremented by one. the value read is the transfer to the di rectly addressed byte indicated. no flags are affected. operation: (pc) (pc) + 2 (direct) ((sp)) (sp) (sp) - 1 bytes: 2 cycles: 2 encoding: 1 1 0 1 0 0 0 0 direct address * instruction timing is identical in flat and large mode
DP80390 instructions set details - 67 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.31. push* 3.31.1. large instruction: push direct function: push onto stack description: the stack pointer is incremented by one. the contents of the indicated variable are then copied into the in ternal ram location addressed by the stack pointer. otherwis e no flags are affected. operation: (pc) (pc) + 2 (sp) (sp) + 1 ((sp)) (direct) bytes: 2 cycles: 3 encoding: 1 1 0 0 0 0 0 0 direct address 3.31.2. flat instruction: push direct function: push onto stack description: the stack pointer is incremented by one. the contents of the indicated variable are then copied into the in ternal ram location addressed by the stack pointer. otherwis e no flags are affected. operation: (pc) (pc) + 2 (sp) (sp) + 1 ((sp)) (direct) bytes: 2 cycles: 3 encoding: 1 1 0 0 0 0 0 0 direct address * instruction timing is identical in flat and large mode
DP80390 instructions set details - 68 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.32. ret * 3.32.1. large function: return from subroutine description: ret pops the pc successively fr om the stack, decrementing the stack pointer by two. program execution continues at the resulting address, generally the instruction immediately following an acall or lcall. no flags are affected. operation: (pc15-8) ((sp)) (sp) (sp) - 1 (pc7-0) ((sp)) (sp) (sp) - 1 bytes: 1 cycles: 4 encoding: 0 0 1 0 0 0 1 0 3.32.2. flat function: return from subroutine description: ret pops the pc successively fr om the stack, decre menting the stack pointer by three. program execution continues at the resulting address, generally the instruction immediately following an acall or lcall. no flags are affected. operation: (pc23-16) ((sp)) (sp) (sp) - 1 (pc15-8) ((sp)) (sp) (sp) - 1 (pc7-0) ((sp)) (sp) (sp) - 1 bytes: 1 cycles: 5 encoding: 0 0 1 0 0 0 1 0 * instruction modified regarding to standard 80c51
DP80390 instructions set details - 69 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.33. reti * 3.33.1. large function: return from interrupt description: reti pops the pc successively fr om the stack, and restores the interrupt logic to accept additional inte rrupts at the same priority level as the one just processed. the stack poi nter is left decremented by two. no other registers are affected; the psw is not automatically restored to its pre-interrupt status . program execution cont inues at the resulting address, which is generally the instru ction immediately after the point at which the interrupt request was detec ted. if a lower or same-level interrupt is pending when the reti in struction is executed, that one instruction will be executed before t he pending interrupt is processed. operation: (pc15-8) ((sp)) (sp) (sp) - 1 (pc7-0) ((sp)) (sp) (sp) - 1 bytes: 1 cycles: 4 encoding: 0 0 1 1 0 0 1 0
DP80390 instructions set details - 70 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.33.2. flat function: return from interrupt description: reti pops the pc successively fr om the stack, and restores the interrupt logic to accept additional inte rrupts at the same priority level as the one just processed. the stack poi nter is left decremented by three. no other registers are affected; the psw is not automatically restored to its pre-interrupt status . program execution cont inues at the resulting address, which is generally the instru ction immediately after the point at which the interrupt request was detec ted. if a lower or same-level interrupt is pending when the reti in struction is executed, that one instruction will be executed before t he pending interrupt is processed. operation: (pc23-16) ((sp)) (sp) (sp) - 1 (pc15-8) ((sp)) (sp) (sp) - 1 (pc7-0) ((sp)) (sp) (sp) - 1 bytes: 1 cycles: 5 encoding: 0 0 1 1 0 0 1 0 * instruction modified regarding to standard 80c51
DP80390 instructions set details - 71 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.34. rl instruction: rl a function: rotate accumulator left description: the eight bits in the accumulator are rotated one bit to the left. bit 7 is rotated into the bit 0 position. no flags are affected. operation: (pc) (pc) + 1 (an + 1) (an) n = 0-6 (a0) (a7) bytes: 1 cycles: 1 encoding: 0 0 1 0 0 0 1 1
DP80390 instructions set details - 72 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.35. rlc instruction: rlc a function: rotate accumulato r left through carry flag description: the eight bits in the accumulator and the carry flag are together rotated one bit to the left. bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 posit ion. no other flags are affected. operation: (pc) (pc) + 1 (an + 1) (an) n = 0-6 (a0) (c) (c) (a7) bytes: 1 cycles: 1 encoding: 0 0 1 1 0 0 1 1
DP80390 instructions set details - 73 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.36. rr instruction: rr a function: rotate accumulator right description: the eight bits in the accumulator ar e rotated one bit to the right. bit 0 is rotated into the bit 7 position. no flags are affected. operation: (pc) (pc) + 1 (an) (an + 1) n = 0-6 (a7) (a0) bytes: 1 cycles: 1 encoding: 0 0 0 0 0 0 1 1
DP80390 instructions set details - 74 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.37. rrc instruction: rrc a function: rotate accumulator right through carry flag description: the eight bits in the accumulator and the carry flag are together rotated one bit to the right. bit 0 moves into t he carry flag; the original value of the carry flag moves into the bit 7 pos ition. no other flags are affected. operation: (pc) (pc) + 1 (an) (an + 1) n=0-6 (a7) (c) (c) (a0) bytes: 1 cycles: 1 encoding: 0 0 0 1 0 0 1 1
DP80390 instructions set details - 75 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.38. setb instruction: setb function: set bit description: setb sets the indicated bit to one. setb can operate on the carry flag or any directly addressable bit. no other flags are affected. 3.38.1. setb c operation: (pc) (pc) + 1 (c) 1 bytes: 1 cycles: 1 encoding: 1 1 0 1 0 0 1 1 3.38.2. setb bit operation: (pc) (pc) + 2 (bit) 1 bytes: 2 cycles: 3 encoding: 1 1 0 1 0 0 1 0 bit address
DP80390 instructions set details - 76 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.39. sjmp instruction: sjmp rel function: short jump description: program control branches uncondition ally to the address indicated. the branch destination is computed by addi ng the signed displacement in the second instruction byte to the pc, after incrementi ng the pc twice. therefore, the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it. note: under the above conditions the instru ction following sjmp will be at 102 h. therefore, the di splacement byte of t he instruction will be the relative offset (0123 h - 0102 h ) = 21 h . in other words, an sjmp with a displacement of 0fe h would be a one-instruction infinite loop. operation: (pc) (pc) + 2 (pc) (pc) + rel bytes: 2 cycles: 3 encoding: 1 0 0 0 0 0 0 0 relative address
DP80390 instructions set details - 77 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.40. subb instruction: subb a, function: subtract with borrow description: subb subtracts the indicated va riable and the carry flag together from the accumulator, leaving the result in the accumulator. subb sets the carry (borrow) flag if a borrow is needed for bit 7, and clears c otherwise. (if c was set before executing a subb instruction, this indicates that a borrow was needed for the previous step in a multiple precision subtraction, so the carry is subtracted from the accumulator along with the source operand). ac is set if a borrow is needed for bit 3, and cleared otherwise. ov is set if a borrow is needed into bit 6 but not into bit 7, or into bit 7 but not bit 6. when subtracting signed integers ov indicates a negative number produced when a negative va lue is subtracted from a positive value, or a positive result when a positive num ber is subtracted from a negative number. the source operand allows four addr essing modes: register, direct, register-indirect, or immediate. 3.40.1. subb a, r n operation: (pc) (pc) + 1 (a) (a) - (c) - (rn) bytes: 1 cycles: 1 encoding: 1 0 0 1 1 r r r 3.40.2. subb a, direct operation: (pc) (pc) + 2 (a) (a) - (c) - (direct) bytes: 2 cycles: 2 encoding: 1 0 0 1 0 1 0 1 direct address
DP80390 instructions set details - 78 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.40.3. subb a, @r i operation: (pc) (pc) + 1 (a) (a) - (c) - ((ri)) bytes: 1 cycles: 2 encoding: 1 0 0 1 0 1 1 i 3.40.4. subb a, # data operation: (pc) (pc) + 2 (a) (a) - (c) - #data bytes: 2 cycles: 2 encoding: 1 0 0 1 0 1 0 0 immediate data
DP80390 instructions set details - 79 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.41. swap instruction: swap a function: swap nibbles withi n the accumulator description: swap a interchanges the low and high-order nibble s (four-bit fields) of the accumulator (bits 3-0 and bits 7-4). the operation can also be thought of as a four-bit rotate in struction. no flags are affected. operation: (pc) (pc) + 1 (a3-0) ? (a7-4), (a7-4) ? (a3-0) bytes: 1 cycles: 1 encoding: 1 1 0 0 0 1 0 0
DP80390 instructions set details - 80 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.42. xch instruction: xch a, function: exchange accumulator with byte variable description: xch loads the accumulator with the contents of the indicated variable, at the same time writ ing the original accumulator contents to the indicated variable. the source/ destination operand can use register, direct, or registe r-indirect addressing. 3.42.1. xch a, r n operation: (pc) (pc) + 1 (a) ? (rn) bytes: 1 cycles: 2 encoding: 1 1 0 0 1 r r r 3.42.2. xch a, direct operation: (pc) (pc) + 2 (a) ? (direct) bytes: 2 cycles: 3 encoding: 1 1 0 0 0 1 0 1 direct address 3.42.3. xch a, @r i operation: (pc) (pc) + 1 (a) ? ((ri)) bytes: 1 cycles: 3 encoding: 1 1 0 0 0 1 1 i
DP80390 instructions set details - 81 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.43. xchd instruction: xchd a, @ri function: exchange digit description: xchd exchanges the low-order nibbl e of the accumulator (bits 3-0, generally representing a hex adecimal or bcd digi t), with that of the internal ram location indirectly addr essed by the specified register. the high-order nibbles (bits 7- 4) of each register ar e not affected. no flags are affected. operation: (pc) (pc) + 1 (a3-0) ? ((ri)3-0) bytes: 1 cycles: 3 encoding: 1 1 0 1 0 1 1 i
DP80390 instructions set details - 82 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.44. xrl instruction: xrl , function: logical exclusive or for byte variables description: xrl performs the bit wise logica l exclusive or operation between the indicated variables, storing the result s in the destination. no flags are affected (except p, if = a). the two operands allow six addre ssing mode combinations. when the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addr essing; when the destination is a direct address, the source can be accumulator or immediate data. note: when this instruction is used to m odify an output port, the value used as the original port data will be read from the output data latch, not the input pins. 3.44.1. xrl a, r n operation: (pc) (pc) + 1 (a) (a) xor (rn) bytes: 1 cycles: 1 encoding: 0 1 1 0 1 r r r 3.44.2. xrl a, direct operation: (pc) (pc) + 2 (a) (a) xor (direct) bytes: 2 cycles: 2 encoding: 0 1 1 0 0 1 0 1 direct address
DP80390 instructions set details - 83 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 3.44.3. xrl a, @ r i operation: (pc) (pc) + 1 (a) (a) xor ((ri)) bytes: 1 cycles: 2 encoding: 0 1 1 0 0 1 1 i 3.44.4. xrl a, # data operation: (pc) (pc) + 2 (a) (a) xor #data bytes: 2 cycles: 2 encoding: 0 1 1 0 0 1 0 0 immediate data 3.44.5. xrl direct , a operation: (pc) (pc) + 2 (direct) (direct) xor (a) bytes: 2 cycles: 3 encoding: 0 1 1 0 0 0 1 0 direct address 3.44.6. xrl direct , # data operation: (pc) (pc) + 3 (direct) (direct) xor #data bytes: 3 cycles: 3 encoding: 0 1 1 0 0 0 1 1 direct address immediate data
DP80390 instructions set details - 84 - all trademarks mentioned in this document http://www.digitalcoredesign.com are trademarks of their respective owners. http://www.dcd.pl copyright 1999-2003 dcd ? digital core design. all rights reserved. 4. c ontacts if any problems are encountered pleas e contact digital core design. headquarters: wroclawska 94 41-902 bytom poland e-mail: i i i n n n f f f o o o @ @ @ d d d c c c d d d . . . p p p l l l tel. : +48 32 282 82 66 fax : +48 32 282 74 37 field office: texas research park 14815 omicron dr. suite 100 san antonio, tx 78245, usa e-mail: i i i n n n f f f o o o u u u s s s @ @ @ d d d c c c d d d . . . p p p l l l tel. : +1 210 422 8268 fax : +1 210 679 7511 distributors: please check h h h t t t t t t p p p : : : / / / / / / w w w w w w w w w . . . d d d c c c d d d . . . p p p l l l / / / a a a p p p a a a r r r t t t n n n . . . p p p h h h p p p

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